Future integrated RF transceiver circuits used in cellular communications devices will have to handle a constantly increasing number of cellular standards and associated frequency bands. The requirements on the frequency tuning ranges of the Voltage-Controlled Oscillators (VCOs) in the Local Oscillator (LO) signal generation subsystem are getting harder to meet while maintaining acceptable performance on other critical specification points like phase noise, current consumption, etc.
The trend towards single die solutions, also referred to as “System on Chip” solutions, forces the RF building blocks to be implemented in “digital” semiconductor processes with poor prerequisites for providing high performance VCO design. This makes it difficult to improve the performance of current solutions to meet the new demands. By “digital” semiconductor processes is meant semiconductor processes optimized for high volume fabrication of large digital circuits at a low cost. These processes do not support special process features like metal-insulator-metal (MIM) capacitors, thick metal layers required by high-Q inductors, and Metal Oxide Semiconductor (MOS) varicaps that facilitate design of high performance analog RF blocks.
A number of new dual-mode VCO designs have been proposed that are addressing the problem how to increase the tuning range compared to that of a state-of-the-art single VCO. Unfortunately, these designs all suffer from degradation of other performance parameters due to the extended tuning range. The use of inductance switching or dual-mode transformer type resonators is associated with degradation of phase noise performance due to unavoidable introduction of additional losses in the resonator circuit.
Alternative Phased-Locked Loop (PLL) solutions using Local Oscillator (LO) frequency dividers with other division ratios than multiples of two reduce the required VCO tuning range but they show a number of unwanted properties regarding waveform duty cycle, quadrature signal output availability, IQ phase accuracy etc.
Using multiple VCOs to cover the required frequency range is a straightforward and flexible solution with the obvious drawback in terms of increased silicon area for those parts of the integrated circuit that contain the VCOs. FIG. 1 illustrates the VCO part of a prior art integrated circuit 100 comprising two separately arranged VCOs 102, 104, each of which VCOs 102,104 comprises a respective inductor 106,108, and a respective capacitor bank 110,112. As illustrated, the use of two VCOs according to the prior art will increase the area of the integrated circuit that is needed as compared to the case when only a single VCO is used. Thus, a disadvantage with the multiple VCOs is the required increased area of the integrated circuit as compared to a single VCO solution. This is especially a disadvantage since the integrated circuits tend to be smaller and smaller in order to fit in smaller and smaller electronic devices. There is also a fabrication cost directly related to the total chip area of the integrated circuit.
Further, the size of the inductor comprised in a VCO or other tuned circuit is not scaling with the technology development and will in the future become a more dominating component on the integrated circuit area.